Nowadays, digital systems are increasingly diversified. How to reduce power consumption of chipsets is a one of main research focuses. Digital synchronous systems usually have one or more sets of clock systems. Clock signals are used to control data movement. The clock system consists of a clock system distribution network and a flip-flop. It consumes greatest power in the chipset. Power consumption can be divided into static power consumption and dynamic power consumption. The dynamic power consumption can be divided into switch power consumption and short circuit current power consumption. The static power consumption mostly is leakage power consumption.
The technique for reducing power can target reducing static power and reducing dynamic power. As the dynamic power consumption always is much greater than the static power consumption, design of circuits mainly focuses on reducing the dynamic power consumption. The most effective approach to reduce power consumption is lowering operation voltage. But lowering the voltage often results in lower speeds. Another alternative is adopting a double-edge trigger design. It can reduce power without decreasing throughput. Thus in practice of circuit design a pulse triggered flip-flop is adopted to reduce system clock loading capacitance and power consumption.
Refer to FIGS. 1 and 2 for the structure of a conventional flip-flop. It includes two latches. Clock signals have a positive edge and a negative edge to control data sampling and holding activities. Referring to FIG. 1, the master latch 1 performs data sampling and the slave latch 2 performs data holding. When in use, data is moved from a data input end (Din) 3 to a data output end (Qout) 4 in sync with an edge signal at a clock signal input end (Clock) 5. A positive edge triggered mode only samples a positive edge signal of the data input end (Din) 3 from the clock signal input end (Clock) 5, and a negative edge triggered mode samples a negative edge signal of the data input end (Din) 3 from the clock signal input end (Clock) 5. Then the data transmission can be accomplished. Thus every complete transaction of data transmission requires two clock signals.
Refer to FIG. 2 for the time series of the flip-flop shown in FIG. 1. A clock signal 6 has a positive edge to sample a data 7 and a negative edge to hold a data 8. Such a phenomenon creates a race trough problem. Hence a time factor that maintaining the flip-flop in normal duty conditions has to be taken into account.
The conventional double edge trigger flip-flop (hereafter is referred to as DETFF) requires only one clock signal 6 to complete the entire transaction of data transmission. A typical DETFF can save data at the positive edge or negative edge of the clock signal. But the transmission delay is longer. The driven loading capacitance at the clock signal input end (Clock) 5 also is greater. Although the clock signal input end (Clock) 5 at the positive edge or negative edge can save data, the original clock signal at the clock signal input end (Clock) 5 must have a double frequency to become a new clock signal. Hence the clock frequency used on the DETFF is one half of the clock frequency of the ordinary single edge triggered flip-flop. But a same data transmission rate can be achieved. As power consumption is proportional to the operational clock frequency, the consumed power also is lower. Hence DETFF is frequently adopted on power reducing designs.
Compared with the single edge triggered flip-flop, the DETFF has a more complex structure and requires a greater chipset size to contain more internal nodes and capacitor exchanging. And it results in the benefit of reducing the frequency is offset.
To address the aforesaid issues other techniques have been developed, such as explicit-pulsed-triggered flip-flop and implicit-pulsed-trigger flip-flop. Both of them can be further divided into a single-edge pulse triggered type and a double-edge pulse triggered type. When the explicit-pulsed-triggered flip-flop is adopted on multiple and serial-and-parallel circuits the pulse generator can be shared, but not so for the implicit-pulsed-trigger flip-flop. Hence total power consumption is much lower when the explicit pulsed-triggered flip-flop is adopted. However, in a serial-and-parallel environment a greater loading capacitance occurs that could result in not able to generate the pulses. As a result, the explicit-pulsed-triggered flip-flop does not provide as much benefits as the implicit-pulsed-trigger flip-flop does. Moreover, with addition of the pulse generator on the circuit, power consumption increases. The implicit-pulsed-trigger flip-flop also has a higher average duty frequency than the explicit-pulsed-triggered flip-flop.
As the pulse-triggered flip-flop provides a less complicated circuit design, it is increasingly accepted in applications of registers. The pulse generator has another important feature, namely control of its operation mode. The traditional pulse generator operates only in one mode. Refer to FIG. 3 for a conventional dual-mode logic circuit. It has a MUX circuit 9A to control two logic circuits, one is a AND logic circuit 9B and another is a XNOR logic circuit 9C. A mode selection signal input E is sent to the MUX circuit 9A as a transmission mode selection signal. Such a logic circuit requires a great number of transistors. Although the circuit is simpler, the loading capacitance of the clock signal input (CLK) 9D is greater and huge power consumption is caused.
On technical development for the design of lower power, multiple duty modes often is a requirement for single-pulse triggered or double-pulse triggered. For instance, at the stage of data synchronization on a data communication circuit, effective duty frequency can be doubled through the double-edge triggered mode. Once the stage of data synchronization is accomplished, the circuit can be switched to single-edge triggered to reduce the power consumption by the effective clock. It the past such a design usually requires pulse generators of two different modes. The single-edge pulse triggered circuit often includes an inverter and an AND or an OR logic gate to generate a positive or negative pulse signal. The double-edge pulse triggered circuit often includes an inverter and a XNOR logic gate and a XOR logic gate, and another MUX circuit to do selections.
On CMOS circuits of the conventional logic circuits, such as those for applications of XOR, XNOR, AND, OR and MUX, the circuits are relatively simple, but they have the problem of threshold voltage loss. The problem of threshold voltage loss is because circuits cannot function at a low voltage and consume a greater amount of power. Such a problem creates other problems on the circuits such as not adequate driving power and short circuit current. In short, adopted the conventional techniques to make a customized circuit are time-consuming and take great efforts. It requires a lot of time to design, execute, customize features and perform integration. There is a need for an improved circuit to provide desired time series specifications, minimum power consumption and enhanced processing speed.